Due to continuing technological innovations in the field of semiconductor fabrication, IC (integrated circuit) manufactures are developing ICs with larger scale of integration, higher device density, lower power consumption and higher operating speeds. Typically, highly integrated circuits are designed using multi-level interconnection structures that are formed from different metal layers as part of a BEOL (back end of line) metallization process. In general, BEOL interconnection structures include intra-level interconnects (metal lines/wiring) and inter-level interconnects (plugs/contacts) embedded in interlayer dielectric (ILD) material.
In conventional BEOL metallization processes, metallic material such as aluminum (Al) was commonly sued to form chip interconnect structures. For example, one conventional BEOL process involves forming an AL metallization layer using a subtractive Al etch process. In general, this process includes depositing a layer of Al on a planarized ILD layer and then etching the AL layer using well-known techniques (e.g., reactive ion etching) to form a wiring/pad pattern for the given metallization layer. The Al etch is then followed by dielectric deposition and planarization to form the ILD layer for the given metallization layer.
As semiconductor devices are scaled down and constructed with increasing smaller design rules, it is undesirable to use aluminum to form metal interconnects because aluminum has a relatively high resistivity which limits chip performance (e.g., operating speed at submicron design rules and beyond. Accordingly, state of the art BEOL techniques for constructing multi-layered metal interconnection lines commonly use metallic material, such as copper (Cu), having low resistivity and high reliability to yield improved performance. Unlike aluminium, however, copper is difficult to pattern using a conventional photolithography/etching techniques, especially when the copper wires are formed according to relatively small design rules.
Accordingly, single and dual damascene methods have been developed to enable formation of highly integrated copper metal interconnect structures. In general, a damascene process includes deposition of a dielectric layer (e.g., ILD layer) and patterning the dielectric layer using standard photolithographic and RIE processes, for example, to define vias holes or trenches (for single damascene) or both via holes and trenches (for dual damascene) in the dielectric layer. After the vias/trenches are formed, a barrier layer is deposited over the patterned dielectric layer to line the exposed sidewalls of the via/trenches and copper deposition process is performed to fill the via/trenches with copper and form the interlevel contracts plugs and/or wiring. The excess copper material is removed from the surface of the wafer by planarizing the wafer surface down to the surface of the ILD layer.
FIG. 1 is a cross-sectional schematic view of a conventional BEOL metallization process for constructing multi-level metal layers on semiconductor wafer (100). In particular, FIG. 1 schematically illustrates a conventional dual damascene method for constructing metal wiring layers on the wafer (100). FIG. 2 is a top plan view of the semiconductor wafer (100) having a conventional layout of chip regions (10) formed on a surface of the wafer. For purposes of illustration, it may be assumed that FIG. 1 schematically illustrates a metallization structure having a repeating pattern in each chip region (10) of the wafer FIG. 1 illustrates an intermediate stage of Mx level fabrication, where a pattern of via holes/trenches (102) are formed in an ILD (inter level dielectric) layer (101) (e.g., silicon oxide) on the upper surface of the wafer (100). The via hole/trench regions (102) include via holes (102b) that are formed in the ILD layer (101) and aligned with lower metal lines (not shown) in the previous metallization level Mx−1. The corresponding trenches (102a) are formed in the ILD layer (101) aligned with the via holes (102b). A conformal liner layer (103) is formed over the entire surface of the wafer (100) to line the exposed surfaces of the ILD layer (101) and to line the bottom and sidewalls of the trenches/vias (102). The liner layer (103) typically comprises a stack of layers including a barrier layer and metallic seed layer sequentially formed on the dielectric layer (101). With copper metallization, the barrier layer may be a metal nitride such as TaN or other suitable conducting material that prevents diffusion of copper material into the dielectric layer and prevents oxidation at the copper material. Typically, a thin etch stop layer (104) is formed between the IDL layers to protect lower metal lines formed in the Mx−1 level.
The metal lines and contacts of the metallization layer Mx are formed by filling the via holes/trenches (102) with copper. The copper fill process is commonly performed using copper electroplating techniques which allow the holes (102b) and overlying line trenches (102a) to be filled at the same time, thus forming dual damascene copper interconnect structures. In order for copper to be deposited on the surface of the wafer (100) by electroplating, the entire wafer surface (100) is covered with a continuous metallic seed layer which serves to conduct bulk electroplating current from the edge of the wafer surface to the inner/central regions of the wafer surface deposition of copper is desired. When a barrier layer such as TaN is used to line the dielectric layer (101), the barrier layer cannot be used to conduct plating current as the barrier material has a high sheet resistance which prevents uniform electrolytic plating on the barrier layer formed over the surface of the substrate. Therefore, the copper seed layer is formed on the barrier layer (via sputtering process or a CVD process) over the entire surface of the wafer to serve as a plating seed layer in an electrolytic plating process.
FIG. 3 illustrates a conventional electroplating apparatus (20) for performing a damascene electroplating process, where a continuous metallic seed layer formed on the wafer surface is used to conduct bulk electroplating current from edge regions to inner/central regions of the wafer surface. In general, the apparatus (20) includes a cathode (21) and anode (22) disposed in electroplating copper solution (23). An electroplating voltage V applied to the cathode (21) and anode (22) causes copper material in the electroplating solution (23) to be plated on the surface of the cathode (21). For damascene electroplating, the cathode (21) is a semiconductor wafer having a continuous seed layer formed on a surface thereof to be plated. For illustrative purposes, it is assumed that the cathode (21) is the semiconductor wafer (100) of FIG. 2 at an intermediate stage of Mx fabrication as depicted in FIG. 1, where the continuous copper seed layer (103) is formed over the entire wafer surface and lining the sidewalls of the vias/trenches (102b/102a). When the wafer (100) is disposed in the apparatus (20) of FIG. 3, the wafer (100) is held in place in the electroplating apparatus (20) by using a clamp that extends around the periphery of the wafer (100) and which forms an electrical contact to the seed layer (103) at the periphery surface regions of the wafer (100) for applying the plating voltage. In this regard the thin metallic seed layer (103) provides a current path to conduct bulk electroplating current from the peripheral surface region of the wafer (100) to the inner/central surface regions of the wafer (100).
Conventional copper electroplating techniques can fill vias and trenches with nanoscale line widths and high aspect ratios. However, such methods become more problematic with decreasing design rules for various reasons. For instance, as devices are scaled down, the line widths become increasing smaller which requires either formation of ultra thin copper seed layers over the diffusion barrier layers, or otherwise use a barrier metal layer that serves as a diffusion barrier and seed layer. However, as the seed layers and barrier layers are made increasingly thinner, the sheet resistance of such layers increase resulting in non-uniformity of copper plating due to a relatively large potential drop of the plating voltage from the wafer edge to the wafer center as a result of the increase resistance along the current path of the seed Layer from the wafer edge to the wafer center
More specifically, FIG. 3 schematically illustrates the electroplating solution having the same resistance R1 at all points between the cathode (21) (wafer) and anode (22) and a resistance R2 of the seed layer from wafer edge (WE) to wafer center (WC). When the resistance R2 is relatively large, there can be a relatively large potential drop (Lower voltage V) at the center of the wafer thereby making Cu plating non-uniform from the between the center and edge regions of the wafer. In particular, as depicted in FIG. 2, when electroplating current is applied to the seed layer in at the wafer edge WE, a very large voltage drop between the edge of the wafer and the center of the wafer can result in very non-uniform plating between the chip regions (10) located at the wafer edges and those chip regions located at the inner/center regions of the wafer. Non-uniformity in copper plating increases with larger wafers (300 mm).